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4.18.0
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  • Linux PCI Bus Subsystem
    • 1. How To Write Linux PCI Drivers
    • 2. The PCI Express Port Bus Driver Guide HOWTO
    • 3. PCI Express I/O Virtualization Howto
    • 4. The MSI Driver Guide HOWTO
    • 5. ACPI considerations for PCI host bridges
    • 6. PCI Error Recovery
    • 7. The PCI Express Advanced Error Reporting Driver Guide HOWTO
    • 8. PCI Endpoint Framework
    • 9. Boot Interrupts
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The Linux Kernel
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  • Linux PCI Bus Subsystem
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Linux PCI Bus Subsystem¶

  • 1. How To Write Linux PCI Drivers
    • 1.1. Structure of PCI drivers
    • 1.2. pci_register_driver() call
    • 1.3. How to find PCI devices manually
    • 1.4. Device Initialization Steps
    • 1.5. PCI device shutdown
    • 1.6. How to access PCI config space
    • 1.7. Other interesting functions
    • 1.8. Miscellaneous hints
    • 1.9. Vendor and device identifications
    • 1.10. Obsolete functions
    • 1.11. MMIO Space and “Write Posting”
  • 2. The PCI Express Port Bus Driver Guide HOWTO
    • 2.1. About this guide
    • 2.2. What is the PCI Express Port Bus Driver
    • 2.3. Why use the PCI Express Port Bus Driver?
    • 2.4. Configuring the PCI Express Port Bus Driver vs. Service Drivers
    • 2.5. Possible Resource Conflicts
  • 3. PCI Express I/O Virtualization Howto
    • 3.1. Overview
    • 3.2. User Guide
    • 3.3. Developer Guide
  • 4. The MSI Driver Guide HOWTO
    • 4.1. About this guide
    • 4.2. What are MSIs?
    • 4.3. Why use MSIs?
    • 4.4. How to use MSIs
    • 4.5. MSI quirks
  • 5. ACPI considerations for PCI host bridges
  • 6. PCI Error Recovery
    • 6.1. Detailed Design
  • 7. The PCI Express Advanced Error Reporting Driver Guide HOWTO
    • 7.1. Overview
    • 7.2. User Guide
    • 7.3. Developer Guide
    • 7.4. Software error injection
  • 8. PCI Endpoint Framework
    • 8.1. Introduction
    • 8.2. PCI Endpoint Core
    • 8.3. Configuring PCI Endpoint Using CONFIGFS
    • 8.4. PCI Test Function
    • 8.5. PCI Test User Guide
  • 9. Boot Interrupts
    • 9.1. Overview
    • 9.2. Issue
    • 9.3. Conditions
    • 9.4. Affected Chipsets
    • 9.5. Mitigations
    • 9.6. More Documentation
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